CS223 Laboratory Assignment 0

Introduction to Lab Techniques and Equipment

Lab date and time:  Tuesday 13:40-16:30

Location: EE 103  (in the EE building, on the left side of 1st floor as you leave the elevator)

Groups: Each student should find a partner and form a 2-person group. The group will work together in the lab. Students who have no lab partner will be assigned one by the TAs.

Preliminary Work 

Read  "Quick startup guide for FPGA and Verilog labs " and "ISE- In Depth Tutorial" (Chapters 2,and 4) documents in the web page.  You are going to use some of  the information in Chapter 2 nd 4 in the lab. You are going to use the Xilinx ISIM  simulator to test your design. Read the section on use of ISIM in the Q"Quick startup Guide"

Task 1: Practice with Logic Gates

Physical gates are built out of transistors, and require physical signals that use correct voltage levels for inputs and produce physical signals with correct voltage levels for outputs. In addition, the transistor circuits that comprise a gate require connections to a voltage supply and to ground.  For example, in the case of 74-series logic circuits used in this lab, the supply voltage (Vcc) must be 5 volts.  In these integrated circuit packages, several gates are contained.  Therefore you must check the connection diagrams given on the link in “IC List” (at http://www.ee.washington.edu/circuit_archive/parts/74ttl/index.html or ask Google specifying  gate number and its function i.e. "7486 xor gate" ) for detailed information, in order to do the following.


1) Using the logic diagram in as a starting point, draw a circuit schematic of the digital circuit you will build.  This should include pin numbers for the inputs and outputs of all the gates you will use, plus power and ground connections.  When you have drawn it, ask the TA to come and check it. Do not proceed to the next step until you have verified that your circuit diagram is correct, and the TA has approved it.


                                                        Fig 1

2) Using your circuit schematic that you made in step 1, build the circuit, following the Suggestions given in the link. Connect up inputs to switches on the logic box. Connect a LED on the logic box to the output of your logic circuit. Don't forget to connect +VCC power and GND ground to the VCC and GND pins on both packages.

3) Make a test probe by connecting another LED on the logic box to one end of a long wire, whose other end will be used to touch circuit points and “see” the logic values (a full voltage level ~5 V will cause the LED to shine brightly, a 0 V level will not light up the LED.  A low-light output from the LED means that the voltage being sensed is in between logic 0 and logic 1, which means something is WRONG with your circuit !

4) Now draw the truth table for the 2-input 2-output logic circuit that you have made, and fill in the left-hand (input) side in standard binary counting order. For each row, apply the input combinations by adjusting the switches, and measure the output. Use this information to complete the truth table, filling in the right-hand (output) side.

5) Compare your measured truth table that you just obtained from the circuit, with the actual truth table of the seatbelt warning circuit.  If there are no discrepancies, then it means that your logic circuit has worked as predicted.  Ask the TA to come and verify this. When the TA has checked your circuit, you are done.

Task 2: Practice with Schematic Entry using Xilinx

1)  Create a Xilinx Prject as described in  "Quick startup guide for FPGA and Verilog labs " and "ISE- In Depth Tutorial" (Chapters 2,and 4).

2) Using the Schematic Entry capability of Xilinx, create a schematic for the circuit in Fig 2.  Name the schematic FullAdd and save.


                                                                 Fig 2

Ask the TA to come and verify your schematic.

2) Test your schematic design by simulation. Use ISIM simulator  of Xilinx software. Prepare Test bench by selecting Verilog Test Fixture in New Source.
The test bench generates all possible combinations  of 3 variablaes. A test bench written in Verilog is given in file t_fulladder.v . Adapt it to your design and simulate your circuit.

// Verilog test fixture created from schematic C:\Users\baray\XilinxVerilogProjects\Adder\fulladder.sch - Tue Feb 19 09:01:06 2013

`timescale 1ns / 1ps

module fulladder_fulladder_sch_tb();

// Inputs
   reg A;
   reg B;
   reg CIN;

// Output
   wire SUM;
   wire COUT;

// Bidirs

// Instantiate the UUT
   fulladder UUT (
        .A(A),
        .B(B),
        .CIN(CIN),
        .SUM(SUM),
        .COUT(COUT)
   );
// Initialize Inputs

       initial begin
        A = 0;
        B = 0;
        CIN = 0;
       
        #10 A=0; B=0; CIN=1;
        #10 A=0; B=1; CIN=0;
        #10 A=0; B=1; CIN=1;
        #10 A=1; B=0; CIN=0;
        #10 A=1; B=0; CIN=1;
        #10 A=1; B=1; CIN=0;
        #10 A=1; B=1; CIN=1;
   
end

endmodule

3) Clean up your lab station, and return all the parts, etc.  Delete the Xilinx Project you created and any files you created today, so that the computer is in the same state that you found it.  Now turn off the computer, and leave your lab workstation for others the way you would like to find it.

NOTES

--Be sure to read and follow the Policies for CS223 labs.