CS223 Laboratory Assignment 2

Modeling Decoders and MUXs in Verilog

Lab date and time:
 Tuesday   March 12, 2013 13:40-17:30 
Location: EE 103  (in the EE building, on the left side of 1^st floor as you leave the elevator)

Groups: Each student should find a partner and form a 2-person group. The group will work together in the lab. Students who have no lab partner will be assigned one by the TAs.

Preliminary Design Report 

A number of tasks in the three subdivisions of today's lab need advance preparation. These advance designs and Verilog models should be prepared in advance with your lab partner, and assembled neatly into a Preliminary Design Report. You should make your report as neat as possible, using A4 paper, with a printed cover page and printed pages for the Verilog codes. Each page of the report should contain just one of the items listed below—do not put more than one design or Verilog code on a page. Each page should have a heading or title that clearly states what is contained on that page. The pages of the report should be stapled together in the upper left-hand corner. If you handwrite anything, it should be neat and legible. All pages, whether printed or handwritten, should have writing only on one side. The contents of the report should be as follows:

(a) A cover page which includes the following (in order from the top): course name and code number, the number of the lab, your group number, the names and ID numbers of each member of the group, and the date of you submit the report.

(b) Dataflow Verilog module  D2to4_decoder from Part A-(a). Prepare a testbench to test your Verilog module.

(c) Design of 3-to-8 decoder from Part A-(e)   Prepare a testbench to test your Verilog module.

(d) Design the decoder circuit for given F(w,x,y) in Part B-(a)

(e) Structural Verilog module for  F(w,x,y) in Part B-(a)

(f) Dataflow Verilog module for 4-to-1 multiplexer with enable. (74153  dual 4-to1 multiplexers with enable)

(g) Design of 8-to-1 MUX with enable, using the 74153 dual 4-to1 multiplexers with enable(dual means that two 4-to-1 multiplexers in one IC  package) and an inverter. Write Verilog code for 8x1 multiplexer using the Verilog code for 4-to- 1 multiplexer with enable. 

(h) Design testbenches for testing your 4-to-1 and 8-to-1 multiplexers designs.

(i)  Implement the G(w,x,y,z)=m( 1,3,4,7,8,9,11,12,15) using an 8-to-1 multiplexer.  Prepare a testbench to test your Verilog module. 

Additional pre-lab work:

Doing the above designs and Verilog programs before coming to lab is crucial in order to quickly and accurately build, test and debug your designs using Xilinx ISE and the DIGILENT board. Obviously, you should endeavor to make accurate and complete designs and Verilog programs, since time spent in advance doing good design work will save you much time later in the lab. Of course you will need a copy of your designs and Verilog programs with you at all times in the lab: to work with, to refer to, to possibly correct and change, to discuss with the TA, to use in debugging. The Preliminary Design Report will be turned in at the start of lab. Therefore, you must make a photocopy of it before you come to the lab, for use by you and your lab partner during the lab. Failure to have a photocopy of your full Preliminary Design Report with you in the lab will result in a deduction of points from the lab grade!

If you are not familiar with the steps in the design flow, using Xilinx ISE (Simulation, Synthesis, Implementation, Generation of Programming File, Downloading to FPGA board), then you should read and study the tutorial Survival Guide for FPGA and Verilog Labs in preparation for your time in lab this week. It contains many things which will be helpful to you at all stages of the lab work. In addition, you should consult the links given in the last 3 labs related with using Xilinx and/or the DIGILENT BASYS-2 board.

Read and study the 3 tasks below (Part A Decoders, Part B Boolean function implementation, and Part C Multiplexers) that you will do in lab this week. If possible, practice the skills that will be required in these 3 parts.

Part A: Decoders (20 points)

Decoders are widely used in digital design, as a building block. Although they themselves can be built with logic gates, their function is often described (and modeled in Verilog) rather than their structure. Decoders can be composed into larger decoders, as you will see in this part of the lab.

A 2-to-4 decoder decodes a 2-bit input binary number by setting exactly one of the decoder's 4 outputs to 1. Unless it has an enable signal, one and only one output of a decoder will ever be 1 at the same time, corresponding to the current value of the inputs. With an enable signal, it is possible to make all the outputs be 0, when the decoder is disabled. When enabled, it behaves as described above. Decoder outputs are mutually exclusive, and in fact are the minterms of the inputs.

• Create a new Xilinx Project to do a), b) and c). Use appropriate names for files and folders, keeping the project in a directory where you can find it later and erase it (at the end of lab).

a) Give the Verilog code which models a 2-to-4 decoder with enable, in the dataflow style. (This means modeling with Boolean equations, using continuous assignment statements.) Name your Verilog module D2to4_decoder . In the port list, let the outputs be first (from least significant to most significant), then the inputs (from most significant to least significant), then the enable signal.

b) Using the Verilog testbench code, verify in simulation that your 2-to-4 decoder with enable is working correctly. (Be sure to compare the order of the ports in your module with the order of the ports in the instantiation of D2to4_decoder in the testbench, to make sure they match 1-to-1.) Note that the testing is complete, using all possible input combinations. When you are convinced that it works correctly, show the simulation results to the TA. Be prepared to answer questions that you may be asked.

c) Now, as you did in previous labs, use the Xilinx design flow to Synthesize,  Create Programming File, and download your 2-to-4 decoder w/ enable to your BASYS-2 FPGA board.

d) Using the switches and LEDs that you have assigned, test your system. When you are convinced that it works correctly, show the physical implementation results to the TA. Be prepared to answer questions that you may be asked. 

e) Design on paper a 3-to-8 decoder using only two 2-to-4 decoders w/ enable, one inverter, and connecting wires. Show the block diagram of this 3-to-8 decoder (using block symbols for the decoders) with the 3 inputs and 8 outputs of the block, and the correct connections of the decoders, inverter and wires inside the block. Use ONLY these components.

• Create a new Xilinx Project to do f), g) and h). Use appropriate names for files and folders, keeping the project in a directory where you can find it later and erase it (at the end of lab).

f) Using the Verilog testbench code you designed in part A, verify in simulation that your 3-to-8 decoder is working correctly. (Be sure to compare the order of the ports in your module with the order of the ports in the instantiation of that module in the testbench, to make sure they match 1-to-1. Also be sure that the names are the same. If necessary, change the names and order of ports in your D3to8_decoder module, so that they correspond perfectly.) Note that the testing is complete, using all possible input combinations. When you are convinced that it works correctly, show the simulation results to the TA. Be prepared to answer questions that you may be asked. 

g) Now, as you did in previous labs, use the Xilinx design flow to Synthesize, Implement, Create Programming File, and download your 3-to-8 decoder to your BASYS-2 FPGA board.

i) Using the switches and LEDs that you have assigned, test your system. When you are convinced that it works correctly, show the physical implementation results to the TA. Be prepared to answer questions that you may be asked. 

Part B: Implementing Boolean functions using decoders. 

Part C: Multiplexers and Boolean function implementation 

A multiplexer (“MUX” for short) is another higher-level building block, used widely in digital design. A M-to-1 multiplexer has M data inputs and 1 data output, and allows only one input to pass through to the output. A set of select inputs determines which input to pass through. If a MUX has an enable input, then it is possible to disable the MUX and force a 0 onto the output, regardless of input values. MUXs can be composed into larger MUXs, as you will see in this part of the lab.

a) Using the Verilog testbench code you have written in preliminary work , verify in simulation that your 4-to-1 MUX with enable is working correctly.  Note that the testing is complete, using all possible input combinations. When you are convinced that it works correctly, show the simulation results to the TA. Be prepared to answer questions that you may be asked. 

b) Set up the circuit you designed G(w,x,y,z)  in preliminary work on breadboard using 74153 dual 4-to-1 multiplexers. Test your cicuit using  switches as input and a a led as output. Show your circuit and test to TA. Be prepared to answer questions that you may be asked.

c) Using the 4-to-1 multiplexer module implement 74153 module and simulate and check that it functions correctly. Show your results to TA.

d) Write the Verilog code for F(w,x,y,z) implementation using the 74153 Verilog module you have written in part (c). Simulate your design and test it with the testbench you designed. Now, as you did in previous labs, use the Xilinx design flow to Synthesize, Implement, Create Programming File, and download your design of G(w,x,y,z) to your BASYS-2 FPGA board.
Using the switches and LEDs that you have assigned, test your system. When you are convinced that it works correctly, show the physical implementation results to the TA. Be prepared to answer questions that you may be asked.

Cleanup !

Clean up your lab station of all papers, trash, parts, wire, etc. Delete the Xilinx Project(s) you created and all the files you created today, so that the computer is in the same state that you found it. DO NOT leave any of your files on a lab computer!! Now turn off the computer, and leave your lab workstation for others the way you would like to find it—clean and organized.

NOTES

--Be sure to read and follow the Policies for CS223 labs.