CS223 Lab Assignment #3

Latches ,Flip Flops and FSM

Lab date and time: 19 March, 2013

Location: EE 103  (in the EE building, on the left side of 1^st floor as you leave the elevator)

Groups: Each student should find a partner and form a 2-person group. The group will work together in the lab. Students who have no lab partner will be assigned one by the TAs.

Lab Assignment

In this lab you will investigate the latch circuits, building flip flop using  two latches, and building a simple FSM using the D-flipflops you have designed.

Preliminary Design Report 

All groups should be prepared to submit their Preliminary Design Report at the start of their lab section time. You report should containing the following items, each starting at the top of a new page:

a) A cover page which includes the following (in order from the top): course name and code number, the number of the lab, your group number, the names and ID numbers of each member of the group, and the date of you submit the report.

b) Write structural  Verilog description of  a level sensitive latch. (Vahid Fig 3.16, page 111). Your  description of the latch should also include a clr(clear) input which will set the latch output to 0 independent of input C. Prepare a test bench for testing your  circuit.

c) Write Verilog description of a  D latch using the Verilog description of  a level sensitive latch in part (b). Prepare a test bench for testing your  circuit.

d) Write Verilog description of a Edge-Triggered D Flip flop (Fig 3.25) using two D latches. Prepare a test bench for testing your  circuit.

e) Design the FSM in problem 3.27 on page 162. Draw the state diagram. Using the state diagram derive the flip-flop input equations of the state controller., and outputs. 

f) Write the Verilog code for the FSM. Use behavioral model for D-flip flops for implementing the state controller of the FSM. Prepare a test bench for testing your  circuit.

g) Write behavioral Verilog code for the FSM in part(e).

IMPORTANT NOTE: The Verilog modules are code, and as with any program code, they should be well-structured, well-commented, use meaningful identifiers, use white space and indentation as appropriate to facilitate understanding, and in summary, should be self-documenting. If code is difficult to understand, it is not self-documenting!

All pages in the report, with the possible exception of a hand-drawn block diagram, should be printed, front side only. All pages should be on white A4 paper. Each page of the report should contain just one of the items listed below—do not put more than one design or Verilog code on a page. Each page should have a heading or title that clearly states what is contained on that page. The pages in the package should be stapled together in the order given, attaching in the upper left-hand corner. The whole package should have a neat, clean, professional appearance.

Of course you will need a copy of your designs and Verilog programs with you at all times in the lab: to work with, to refer to, to possibly correct and change, to discuss with the TA, to use in debugging. Therefore, you should make a photocopy of the Preliminary Design Report, for you and your partner to use during the lab.

In-Lab Demos (60 points)

You should come to lab fully prepared. Your Preliminary Lab Report will be submitted when you enter, so you must make a photocopy for yourselves, for your group to use during the lab. Failure to have a photocopy of your full Preliminary Design Report with you in the lab will result in a deduction of 5 points from the lab grade!

You are advised to arrive with the problem above fully implemented and tested and ready to work. Your grade will be based on the following:

a) You will also be asked to do simulation, using the testbench modules you created, for each of the original Verilog modules starting with level sensitive latch, D flip flop and FSM. 

b) You may be asked to modify your design (the new specification will be given to you in the lab), as proof that you understand what you are doing and can respond to changes in the specification real-time. This may involve changes in the Verilog modules for the FSM. 

c) For the behaviour Verilog description of your FSM  do the Xilinx design flow (Synthesize, Implement, Create Programming File, and Download) to realize your design on the Digilent FPGA board. Use one of  push buttons to simulate clock. In order to avoid errors use button press synchronizer to connect the push button output to clock input of the FSM. Using the switches and LEDS  that have been assigned, test your system. When you are convinced that it works correctly, show the physical implementation results on the BASYS-2 board to the TA, who will grade the demo of your project.

Reminder: One push of the push-button switch you chose for clock input should result in one synchronized de-bounced clock pulse to the flip-flops, by means of the special circuit you designed in part (h) above. DO NOT connect the push-button directly to the flip flop clock inputs!

d) Finally, the TA will ask each lab partner questions to check your knowledge and understanding of the project and Verilog, and you will receive a grade according to your answers. As a result, your grade and your partner’s grade might not be the same grade, depending on your answers to the oral questions.

Cleanup !

Clean up your lab station of all papers, trash, parts, wire, etc. Delete the Xilinx Project(s) you created and all the files you created today from the lab computer, so that the lab computer is in the same state that you found it. DO NOT leave any of your files on a lab computer!! Now turn off the computer, and leave your lab workstation for others the way you would like to find it—clean and organized.

NOTES

--- Be sure to read and follow the Policies for CS223 labs.

--- An extensive tutorial is posted online at http://www.cs.bilkent.edu.tr/~oonder/CS223/. You will find that this written tutorial provides vital information on how to create a project in Xilinx ISE software and how to download it into the Digilent BASYS-2 FPGA board.

---Note that on older BASYS-2 boards, there is one mistake in the letters printed on the Digilent board. The pin number printed for SW0 is mistakenly written as M4, but actually it should written as P11, because it is connected to P11. You can make this change easy to remember by writing a small sticker and attaching it to the board by SW0

-- The PCs in the lab contain the Xilinx and Digilent software, installed. You should use your own laptop computer to develop, test, debug and make ready the project before you come to the lab. On the day of your lab, you will be much better off to bring your own laptop computer with you, and to demonstrate the assignment using it. The idea is for your group to be able to bring your fully tested, debugged and working systems to lab, only to be graded.