CS223 Lab Assignment #4

16-Button Keypad to 7-Segment Display

Lab date and time:

·        Tuesday   March 26, 2013

·        EE 103  (in the EE building, on the left side of 1st floor as you leave the elevator)

Groups: Each student should find a partner and form a 2-person group. The group will work together in the lab. Students who have no lab partner will be assigned one by the TAs.

Lab Assignment



In this lab, we will use a  16-key keypad on the experiment set. The keypad is arranged as a  has 4 rows and 4 column arranged as a matrix as shown in the . Keys are selected by their row selects RB4,RB5,RB6,RB7 and column selects RB0,RB1,RB2,RB3.  For example key 5 if pressed will connect RB5 and RB1, and key 6 if pressed will connect RB5  and RB2  The  pressed  key will be identified as combination of a row  and a column. An example of a 12 key keypad is given  in the book (Example 2.26 page 77 ).   The row and column outputs will be connected to a converter which will generate the code for each key.  In order to use the keypad with BASYS board the rows of the keypad will be set  to 1 sequentially as shown in Fig 2 .  The signals R0,R1,R2,R3 are the row  drivers generated by the FPGA on the BASYS board. When a key is pressed the corresponding row will be connected to one of column lines. If the rows are connected to JB connector and columns tor JA connector   of  the BASYS board than the key pressed will be detected by the FPGA and the converter circuit will convert that value to its  4-bit Hex code.

               Fig41.jpg

                                                                   Figure 1 Keyboard

You will design the column driver in Verilog which will generate signals R0, R1, R2, R3 as shown in Fig 2. You will also design the module to drive the hexdisplay.  

                                                                                        Figure 2                                                       

  The purpose of the hex2led module (see Figure 3) is to display the hexadecimal equivalent of the number Hex on a 7-segment display.

There are four 7-segment displays on the BASYS-2 board. Therefore we must select which display will be used. AN0, AN1, AN2 and AN3 are used to select the display digit(s). Some examples are: If AN[0:3] ="0111" then the 1st display (on the left) is selected. If AN[0:3] = "1011" then the second display is selected. If AN[0:3] = "1100" then right-hand two displays are selected. Note that in the BASYS-2 board the display select signals are active low. You can read about this and other 7-segment display functions in Survival Guide for FPGA and Verilog Labs and in the documentation about the BASYS-2 board.

By means of those 7-bit dis[6:0] outputs, the key which is pushed will be displayed on the hex display of the BASYS board.. The hex-to-led decoder will have 4-bit input and the 7-bit output, for the display value, as shown below. In addition, you should select which display you want the value to appear on, using the AN outputs, as described above. To just show the output on one display, you need to turn off the other 3 displays using the an outputs (“an” is short for anode). This can be done under the control of the sin signal (for “select input”). The 2-bit sin signal controls which of the 4 an outputs will be active.


Figure 3 hex2led Module

 

Table 2 (below) gives the conversion for all 16 input combinations. (Note: the table on p. 73 of the book does NOT give all 16 output values!]

Hex

Display

Hex

Display

Hex

Display

Hex

Display

0000

0

0100

4

1000

8

1100

c

0001

1

0101

5

1001

9

1101

d

0010

2

0110

6

1010

A

1110

E

0011

3

0111

7

1011

b

1111

F

Table 1  Hex versus 7-segment Display output

You can view the variable dis[6:0] as being equal to the binary number “gfedcba”, i.e. dis[6:0]= “gfedcba”. For example if dis[6:0] = "0001000", then d=1, and a=b=c=e=f=g=h=0. In this case an 'A' is displayed on the 7-segment display. Note that a LED segment turns ON (shines) if the corresponding bit is “0”, and it turns OFF if the corresponding bit is “1”.

The LED layout of a seven segment display is given in Figure 4. To know more about seven segment displays and how to use them, read Survival Guide for FPGA and Verilog Labs


Figure 4

 

Before Lab:

--Obtain a Digilent BASYS-2 board and install the Xilinx ISE software to your personal laptop computer.

--Write the Verilog code for the module row driver and converter. Plan and prepare the testbench and the data needed, in order to test your module.

--Write the Verilog code for the module hex2led. Plan and prepare the testbench and  the data needed, in order to test your module.

--Write a top-level module of Verilog code overall_key2display which will combine the Row Driver converter code and hex2led code in a 2-level hierarchy. [Note that in doing this, you will use two Verilog modules as building blocks in a higher-level Verilog module. So your design for this part will be a 2-level hierarchy of Verilog modules.] Plan and prepare the testbench and the data needed, in order to test your module.

--Make the Preliminary Design Report and its photocopy (see below for specification).

Preliminary Design Report (40 points)

All groups should be prepared to submit their Preliminary Design Report at the start of their lab section time. You report should containing the following items, each starting at the top of a new page:

a) A cover page which includes the following (in order from the top): course name and code number, the number of the lab, your group number, the names and ID numbers of each member of the group, and the date of you submit the report.

b) Explanation of both the function and the structure of the row driver and converter circuit, Verilog code for the row driver and converter. Verilog code for module hex2led . Test benches for all modules.

 

IMPORTANT NOTE: The Verilog modules are code, and as with any program code, they should be well-structured, well-commented, use meaningful identifiers, use white space and indentation as appropriate to facilitate understanding, and in summary, should be self-documenting. If code is difficult to understand, it is not self-documenting!

All pages in the report, with the possible exception of a hand-drawn logic diagram, should be printed, front side only. All pages should be on white A4 paper. Each page of the report should contain just one of the items listed below—do not put more than one design or Verilog code on a page. Each page should have a heading or title that clearly states what is contained on that page. The pages in the package should be stapled together in the order given, attaching in the upper left-hand corner. The whole package should have a neat, clean, professional appearance.

Of course you will need a copy of your designs and Verilog programs with you at all times in the lab: to work with, to refer to, to possibly correct and change, to discuss with the TA, to use in debugging. Therefore, you should make a photocopy of the Preliminary Design Report, for you and your partner to use during the lab.

 

In-Lab Demos (60 points)

You should come to lab fully prepared. Your Preliminary Lab Report will be submitted when you enter, so you must make a photocopy for yourselves, for your group to use during the lab. Failure to have a photocopy of your full Preliminary Design Report with you in the lab will result in a deduction of 5 points from the lab grade!

You are advised to arrive with the problem above fully implemented and tested and ready to work. Your grade will be based on the following:

a) You will also be asked to do simulation, using the testbench modules you created, for one of the original Verilog modules (the TA will choose which one.)

b) You will be asked to create a new project in Xilinx, modifying your design (the new specification will be given to you in the lab), as proof that you understand what you are doing and can respond to changes in the specification real-time. This may involve changes in the Verilog modules, in their Verilog testbench modules, in the User Constraint file (including bringing in MCLK from pin B8 to go to DISP's clk signal), or in the overall design. You will need to integrate all the parts of the system together in overall_key2display, in order to implement the overall system design of part f) in your Preliminary Design Report. 

Do the Xilinx design flow (Synthesize, Implement, Create Programming File, and Download) to realize your design on the Digilent FPGA board. Using the connecters given or experiment board  test your system. When you are convinced that it works correctly, show the physical implementation results to the TA, who will grade the demo of your project.

Reminder: The inputs include keys for * and #, but the 7-segment displays don't have that capacity. So in your overall test, when a * is pushed  the 7-segment display should show E. When a # is pushed (on the BASYS board, on the push-button it corresponds to), the 7-segment display should show F.

c) Finally, the TA will ask each lab partner questions to check your knowledge and understanding of the project and Verilog, and you will receive a grade according to your answers. As a result, your grade and your partner’s grade might not be the same grade, depending on your answers to the oral questions.

Cleanup !

Clean up your lab station of all papers, trash, parts, wire, etc. Delete the Xilinx Project(s) you created and all the files you created today from the lab computer, so that the lab computer is in the same state that you found it. DO NOT leave any of your files on a lab computer!! Now turn off the computer, and leave your lab workstation for others the way you would like to find it—clean and organized.

NOTES

--- Be sure to read and follow the Policies for CS223 labs.

--- An extensive tutorial is posted online at http://www.cs.bilkent.edu.tr/~oonder/CS223/. You will find that this written tutorial provides vital information on how to create a project in Xilinx ISE software and how to download it into the Digilent BASYS-2 FPGA board.

---Note that on older BASYS-2 boards, there is one mistake in the letters printed on the Digilent board. The pin number printed for SW0 is mistakenly written as M4, but actually it should written as P11, because it is connected to P11. You can make this change easy to remember by writing a small sticker and attaching it to the board by SW0

-- The PCs in the lab contain the Xilinx and Digilent software, installed. You should use your own laptop computer to develop, test, debug and make ready the project before you come to the lab. On the day of your lab, you will be much better off to bring your own laptop computer with you, and to demonstrate the assignment using it. The idea is for your group to be able to bring your fully tested, debugged and working systems to lab, only to be graded.