|
WEEK |
BEGINS |
TOPICS COVERED |
READINGS |
LABS/HW DUE |
|
1 |
4/2/2013 |
Introduction, digital and binary data representation |
Digital Design, Chapter 1 |
|
| 2 | 11/2/2013 | Switches, transistors, logic gates, Boolean algebra | DD 2.1-.2.5 | |
|
3 |
18/2/2013 |
Truth tables, canonical forms, combinational design process, examples |
DD 2.6-2.7 | |
|
4 |
25/2/2013 |
Optimization of combinational circuit design |
DD 6.2, 6,3 |
Lab #0 |
|
5 |
4/3/2013 |
Decoders and MUXes, non-ideal behavior, Verilog modeling |
DD 2.8,-2.10, |
Lab #1 HW #1 |
|
6 |
11/3/2013 |
Latches & flip-flops, basic register, clocking, FSMs |
DD 3.1, 3.2, 3.3 |
Lab#2 |
|
7 |
18/3/2013 |
Controller design, examples, non-ideal behavior, Verilog modeling |
DD 3.4, 3.5, 3.8 |
Lab#3 |
|
8 |
25/3/2013 |
Registers, adders, comparator, multiplier, |
DD 4.1-4.5 |
HW #2 Lab#4 |
|
9 |
1/4/2013 |
Signed numbers, subtractors, ALUs, shifters, counters, timers, register file, Verilog modelingMidterm exam |
DD 4.6-4.10, 4.13 |
No Lab
|
|
10 |
8/4/2013 |
High-level state machines HLSM, RTL design process, examples |
Lab #5 |
|
|
11 |
15/4/2013 |
RTL design (continued), clock frequency, behavioral design, |
DD 5.4-5.7 |
Lab #6 |
|
12 |
22/4/2013 |
Memory,RAM, ROM, Verilog modeling |
DD 5.8-5.10, 5.13 |
No Lab |
|
13 |
29/4/2013 |
Optimizations and tradeoffs |
DD Chapter 6 |
Lab #7 HW #3 |
|
14 |
6/5/2013 |
Physical implementation on ICs |
DD Chapter 7 | Lab #8 |
|
15 |
13/5/2013 |
Reserved |
|
|
Grading Plan: Homeworks (15%), Quizzes (15%), Labs (15%), Midterm (25%), Final (30%)