ENERGY EFFICIENT FPGA ACCELERATORS FOR GRAPH ANALYTICS APPLICATIONS
Principal Investigator: Mustafa Ozdal
Funding: European Commission H2020-MSCA-IF
Budget: € 145,845.60
Duration: April 2016 - 2018
Abstract
It is reported that data centers today consume significant
portion of the global electricity usage. This is expected to increase in the
upcoming years as the amount of data processed in the cloud increases
substantially. An effective way for data centers to achieve better performance
and energy efficiency is to perform computation on specialized processing
elements. Field programmable gate arrays (FPGAs) enable customization of logic
after manufacturing to achieve better energy efficiency compared to general purpose
processors. Today, prominent hardware and software companies are investing in
data center solutions that integrate FPGAs with CPUs, and significant
performance and energy improvements have been demonstrated for several data
center applications. However, the main barrier for wide spread adoption of
FGPAs in data centers is the cost of programming, which typically requires
months of development time by hardware engineers. The objective of this project
is to lower this barrier for emerging graph applications. The basic idea is to
use an abstract interface that allows a domain expert to describe an
application as a set of functions defined per vertex and/or edge. We have
developed a customizable implementation template that allows users to specify C++
functions to describe different graph applications. The developed template
hides from users many low-level implementation details such as parallelization,
pipelining, synchronization, memory access optimization, race and deadlock
avoidance. This helps bridge the gap between high level application
descriptions and costly hardware implementations. Our experiments show that the
accelerators developed using the proposed template can lead to significant
energy efficiency improvements compared to multi-core server CPUs.
Work Done
An accelerator template has been developed using
SystemC. A well-defined interface was developed for users to specify different
graph applications using plain C++ constructs and functions. After these
user-defined constructs and functions are plugged into the developed accelerator
template, hardware can be generated using standard industrial flows. In
experiments, several graph applications were modelled using this template, and
significant reductions in power consumption were demonstrated compared to
multi-core CPUs. Furthermore, collaboration with industry researchers has been
set up to port the proposed accelerator template to an emerging data center
platform that integrates FPGAs with CPUs. Three journal articles were published
during this project and another one is in preparation. Initial results were
presented in a conference, a workshop, and a seminar.
Contributions
This project has contributed to the state of the art
as follows. First, an accelerator architecture is proposed that is specifically
targeted at graph applications. This architecture was published in a journal
article (M. Ozdal, et. al, “Graph Analytics Accelerators for Cognitive
Systems”, IEEE MICRO, pp 42-51, March 2017). Second,
a high-level design framework was developed to make it easy for domain experts to
develop accelerators. This framework was published in another journal article (A.
Ayupov, et. al, “A Template-Based Design Methodology for Graph-Parallel
Hardware Accelerators”, IEEE Transactions on Computer-Aided Design of
Electronic Systems, pp 420-430, May 2017).
Third, this template was ported to an emerging FPGA platform. An article on
this topic is currently under preparation.
Recently,
there has been a shift in data center platforms towards customizable hardware such
as FPGAs to achieve energy efficiency and performance improvements. However, most
domain experts cannot effectively utilize these FPGAs because of the steep learning
curve involved in hardware design. This project fills this gap for graph
applications by making it easy to develop accelerators without hardware
knowledge. This is especially helpful for small/medium companies to utilize these
FPGAs without incurring high engineering costs. Also, improving FPGA
utilization in data centers have the potential to significantly reduce the electricity
consumption of data centers.