CS223 Laboratory Assignment 10

Design Project: Digital Clock and Stopwatch

Lab dates and time:

Location: LAB 103 (in the new EEE building, next to and down from the EA Building)

Groups: Each student should work with a partner in a 2-person group (unless permission for a 1-person or a 3-person group has been given).

Duration: The last lab of the semester is a multi-week design project, bringing together the skills of digital design in a medium-sized project. You and your lab partner will need to work together both in the lab and outside it, in order to achieve the goals of this project in the time allowed.

[Week1] Problem Specification

In this lab, you will continue to explore the capabilities of the Xilinx ISE environment. You will learn to design, model, simulate, implement, download and test sequential circuits. The main assignment is to use Verilog for designing a digital clock and stopwatch, modeling it as described below.  The Verilog model will be simulated using the ISim software, and downloaded into the Digilent FPGA board and tested, to verify correctness.

Your model for the system should have four outputs, which are the 4 display units (7-segment) on the Digilent board. When in Clock mode, they show hour on the left 2 digits, and minutes on the right 2 digits, with the colon in between also on. (Note: time should be displayed using the 24-hour format.) In Stopwatch mode, the 4 digits display seconds (up to 99), tenths and hundredths of seconds, with the dot in between also on.

The modes are controlled by inputs as follows: SW7: reserved for future use; SW6: 0= Stopwatch mode, 1= Clock mode.

In Stopwatch mode, SW5 =0 is for Operate, SW5= 1 is for History. When operating, BTN3 pushed once starts the stopwatch, and pushing it again stops the stopwatch. Starting the stopwatch begins the timing from the current value. When BTN0 is pushed, the current value is cleared to zero. In History mode, the options are Save History (00), Reset History (01), and Display History (10), depending on the values of SW2 and SW1. The minimum time and maximum time from previous usages are stored and can be displayed, or reset, and the current stopwatch time can update the min or max if its value is appropriate (i.e. greater than the previous maximum, or less than the previous minimum). To save the current value to history (i.e to update the saved history values), the BTN3 button is pushed, and the history values are updated as appropriate, using the current stopwatch time. (Note that the first time a stopwatch time is saved to history after a reset, it will become the new minimum AND the new maximum.) Reset History is commanded with pushing BTN3, and all stored history values are cleared to zero. When displaying history, the stored values are displayed and scrolled through by repeatedly pushing BTN3.

In Clock mode, SW5 is reserved for future use, and SW4 =0 means to display the clock time, and SW4= 1 is to set the clock time.

When setting the time, BTN0 chooses hour or minute to be set, and scrolls circularly between them. When hour is selected, the displays of the minute digits are turned off, and the hour digits blink on-off at 0.5 Hz. The vice-versa is true when minute is selected. SW0 chooses whether the value will be incremented up or down (by its physical position), and BTN3 pulses will increment (or decrement) the value of the time displayed (and of course, the value which is stored).

At the startup of the digital clock/stopwatch, all values are reset to zero.

In addition to the above, there are more requirements to do for the second week of the lab. If you plan to finish the lab from the first week, you have to implement everything described for week 1 and week 2.

[Week1] Advance Work (before the 1st week lab), At Lab time (1st week), and During the In Between Week

Design the digital clock and stopwatch as specified above. The basic design should be done in Verilog, as a 2-level hierarchy of 3 modules: Lab10 (the overall module), control unit, and datapath (but if the datapath itself instantiates modules, then of course the overall heirarchy will have more than 2 levels). For the overall Lab10 module, you will need to use structural Verilog. For the control unit, you should use behavioral style Verilog, as taught in the class and in the supplementary pages on reserve in the library. For the datapath, you are free to use any Verilog style you like, including Behavioral (which means all is modeled in one module), Structural (which means lower-level modules are instantiated and connected with wires inside the datapath), or Mixed.

Check your design carefully, to increase your chance of success in the lab. You will want to build and test, build and test, incrementing the functionality at each stage. . [Remember: research has consistently proven that the number of errors in software is in direct proportion to the size of the program.]

[Week2] Problem Specification 2

Additional Functionality: Add a calendar function to the clock/stopwatch, so that it becomes as clock/stopwatch/calendar. When slide switch SW7 is set to 1, the system is in calendar mode, but when set to 0, it is in Clock or Stopwatch mode. The calendar should automatically reset to 01.01.2000 when powered on. Like any calendar, it should imcrement to the next date after midnight, increment to the next month after the last day in the present month (28, 30 or 31), and should increment to the next year after December 31st. In Calendar mode, SW5 =0 is Show Date mode, but SW5 =1 is Set Date mode. When showing the date, either the year shows on all 4 displays, or else the day and month show, with a dot between them (example, 25.12 for the day of the lab). These two displays are scrolled by repeatedly pushing a pushbutton switch (BTN3). In Set Date mode, BTNO pulses choose what to display and set (day, month, or year) by scrolling through them. In Set Date mode, whatever is displayed should be displayed in its normal position, it should be flashing on-off at 0.5 HZ, and only it should be displayed. To make changes, pushbutton BTN3 is used, with each pulse changing the current value by 1. Slide switch SW0 determines if the change is an increment (when in the “up” position) or a decrement (when in the “down” position). The value shown is also recorded at the same time.

At the start of lab time on Thursday May 13, there will be some additional changes announced on the board.

[Week2] At Lab time (2nd week)

You should come to lab fully prepared. Bring any documents with you, for your group to use during the lab. You should definitely bring all the Verilog code that you have written for past labs, as a “library” of potentially useful functions, as well as the code you have developed for Lab 10 and your working Digilent board. You should arrive with the Lab10 project (above) fully implemented and tested and ready to show to the TAs. When you arrive in lab, there will be a modification of the project specification written on the board for your section. You must implement this real-time in the lab, and show a working demo of it to the TA before the end of lab time.

Physical Circuit with FPGA (80 points)

a)     At the start of your lab on the final day of this project, you will be asked to create a new project in Xilinx, modifying your design (the new specification will be given to you in the lab), as proof that you understand what you are doing and can respond to changes in the specification real-time. This may involve changes in the design, in the ASMD, in the Verilog, in the User Constraint file, and in the testing. You will show the TA your modified working circuit in the Digilent board, and the demo of your new project will be graded.

b)     Finally, the TA will ask each lab partner questions to check your knowledge and understanding of the project and Verilog, and you will receive a grade according to your answers.

As a result, your grade and your partner’s grade might not be the same, depending on your answers to the oral questions.

Cleanup!

Clean up your lab station, and return all the parts, etc. If you used a lab computer, delete the Xilinx Project you created and any files you created today, so that the computer is in the same state that you found it. Now turn off the computer, and leave your lab workstation for others the way you would like to find it.

Final Lab Report (20 points)

After you have showed your demo in the final week of lab, you should “freeze” your code, that is make a copy of what it was at the time of the demo. You must email this code immediately to the TA (oonder [at] cs....) so that it can be compared for copying against other groups' Verilog code. In addition, this code, together with the sections listed below, should be a part of your Final Report for Lab 10. You will submit this document by 16:00, the next day after you show your demo (no later than 16:00 at Friday May 14th, 2010). It must be submitted to the mailbox (in the Computer Engineering Dept headquarters) of the TA (mailbox named as ONDER). LATE reports will be penalized, so be careful to get it into the box by the deadline.

You should prepare the Final Report for Lab 10 (as described below, and in the Notes at the bottom, and in the Lab Policies) to be submitted after the lab is finished. Your Final Report for Lab 10 should contain the following items, each starting at the top of a new page:

The Verilog modules are code, and as with any program code, they should be well-structured, well-commented, use meaningful identifiers, use white space and indentation as appropriate to facilitate understanding, and in summary, should be self-documenting. If code is difficult to understand, it is not self-documenting!

All pages in the report, with the possible exception of the ASMD diagrams and block diagrams, should be printed, front side only. Any handwritten pages must be neatly drawn, but printed is preferable. All pages should be on white A4 paper. The pages in the package should be stapled together in the order given, attaching in the upper left-hand corner. The whole package should have a neat, clean, professional appearance.

Notes .

--It is strongly recommended that you prepare, verify, debug your designs in advance, and that you simulate them to prove they work BEFORE coming to lab for the 2nd week. Although the TA's and instructor will be available to help with questions and problems during the first week lab, the lab time in the 2nd week will be primarily for modifying your design, and demonstrating it to the TA's. Design and debugging should be done in advance as much as possible.

-- The PCs in the lab contain the Xilinx and Digilent software, installed, but these computers are extremely slow. You should use your own laptop computer to develop, test, debug and make ready the project before you come to the lab. On the day of your lab, you will be much better off to bring your own laptop computer with you, and to demonstrate the assignment using it. The idea is for your group to be able to bring your fully tested, debugged and working systems to lab, only to make some small changes and then be ready to be graded.

-- As with all software code, your program should be well structured, well commented, and use meaningful labels to be self-documenting. Good style also suggests use of bold type (for reserved words), alignment and white spacing for easy readability. You should use default values in coding any combinational circuitry, to avoid unwanted latches when synthesizing. Besides these style features, your program should make good choices for modeling the control unit and datapath in an efficient way. You should seek to use the high-level features of the language whenever possible (see Verilog Resources page for more info).

-- An extensive tutorial is posted online at http://www.cs.bilkent.edu.tr/~oonder/CS223/ . You will find that this written tutorial provides vital information on how to create a project in Xilinx 11 and how to download it into the Digilent BASYS 2 FPGA board.

-- Information about Verilog (including about simulation and testbench modules), and about Algorithmic State Machine with Datapath (ASMD) is available in the Reserve Room of the main campus library.

-- Be sure to read and follow the Policies for CS223 labs.