CS223 Laboratory Assignment 6

CS223 Laboratory Assignment 6

4-Bit Carry Look-ahead Adder with 7-Segment Display Outputs

Lab date and time:

Section 1: 03/11/2009 13:40-17:30
Section 2: 06/11/2009 13:40-17:30
Section 3: 02/11/2009 13:40-17:30
Section 4: 06/11/2009 08:40-12:30

Location: LAB 103 (in the new EEE building, next to and down from the EA Building)

Groups: Each student should work with a partner in a 2-person group.

ASSIGNMENT

This week, you will design a 4-bit adder whose outputs are displayed using 7-segment displays. The adder itself should be a Carry Look-ahead Adder, which implements the carry chain much faster (but with more hardware) than the Ripple Carry Adder shown in class. [You will need to do research in books or on the Internet to learn about carry look-ahead adders and their implementation, and explain how they work in your Preliminary Design Report.]

The circuit will have 3 data inputs (A, B and Cin). A and B should be implemented using slide switches, and Cin implemented using a push-button switch. When the Cin switch is depressed, the carry-in bit is 1, and when it is not, the carry-in bit is 0. The circuit also has one control input Digit (also implemented with a push-button switch), which is used to select which output digit should be displayed. When the Digit switch is depressed, the most significant digit (MSD) of the sum should be displayed, and when it is not, the Least Significant Digit (LSD) of the sum should be displayed. The sum should be displayed as 2 hexadecimal digits, each on a separate 7-segment display, using characters 0…9, A, b, C, d, E, F to represent the number. [In order to give the correct values of the LEDs in the 7-segment display, you will need to do research to learn about HEX-to-7-segment decoding.]

To design this 4-bit adder, you should make a hierarchical model, using several Verilog modules for significant sub-functions, and then instantiating them inside the overall module (named Lab6) which models the entire system. You have freedom to model it any way your group decides is best, within the following constraints. You must write and include at least the following Verilog modules:

· Lab6 (A, B, Cin, Digit, …..) a structural (or mixed) style Verilog module, at the top of the hierarchy

· 4_bit_CLA (A, B, Cin, …………) a structural style Verilog module which implements a 4-bit carry look-ahead adder

· 4bit_2_to_1_MUX (X, Y, Digit, OUT) using any Verilog style

· HEX_to_7segment (………,a,b,c,d,e,f,g) a dataflow style Verilog module which implements the decoding functions needed to drive a 7-segment display. Its input is a 4-bit hexadecimal value, and its outputs are the 7 values for the LEDs in the 7-segment display.

Before Lab:

0. Obtain a Digilent BASYS 2 board and install the Xilinx ISE 11 software to your personal laptop computer (see Lab 5 for details).

Design the project, using hierarchical decomposition, to obtain the components that will comprise the overall solution. Then write the Verilog code for each of the components, making each a module. Assemble the modules in the hierarchy, to comprise the overall design. Using Xilinx ISE, make a project and add the Verilog source modules, and check for syntax and semantic errors.
Test each of your Verilog modules individually, moving from modules low in the hierarchy upward to the top. Rather than physically download and test on the Digilent board, you should test using simulation, by creating a testbench within Xilinx. When the top-level module Lab6 is fully working, you are ready to create a user constraint file and download it to the Digilent board for manual verification.
When all is working with your design, write up the Preliminary Lab Report as described below.

Preliminary Lab Report (30 points):

At the start of lab, you should submit a Preliminary Lab Report, containing the following items, each starting at the top of a new page:

· Cover page, containing the course number and course name, the Lab number and lab name, the date, the names, ID numbers, and section numbers of each lab partner

· Explanation of both the function and the structure of the carry look-ahead adder (CLA) in general, as well as a logic diagram for your 4-bit CLA (it should match 1-to-1 the Verilog module that models it)

· Verilog code for module 4_bit_CLA, which implements your CLA (it should match 1-to-1 the logic diagram in the previous section)

· Verilog code for the module 4bit_2_to_1_MUX, which implements your 4-bit 2-to-1 multiplexor

· Verilog code for the module HEX_to_7segment decoder

· Verilog code for any other modules you create

· Verilog code for the overall module Lab6.

The Verilog modules are code, and as with any program code, they should be well-structured, well-commented, use meaningful identifiers, use white space and indentation as appropriate to facilitate understanding, and in summary, should be self-documenting. If code is difficult to understand, it is not self-documenting!

All pages in the report, with the possible exception of a hand-drawn logic diagram, should be printed, front side only. All pages should be on white A4 paper. The pages in the package should be stapled together in the order given, attaching in the upper left-hand corner. The whole package should have a neat, clean, professional appearance.

During Lab (70 points): You should come to lab fully prepared. Your Preliminary Lab Report will be submitted when you enter, so make a photocopy for yourselves, for your group to use during the lab. You should arrive with the problem above fully implemented and tested and ready to show to the TAs for grade. Your grade will be based on the following:

a) You will also be asked to do simulation, using the testbench modules you created, for one of the original Verilog modules (the TA will choose which one.)

b) You will be asked to create a new project in Xilinx, modifying your design (the new specification will be given to you in the lab), as proof that you understand what you are doing and can respond to changes in the specification real-time. This may involve changes in the Verilog, in the simulation testbench, in the User Constraint file, etc. You will show the TA your modified working circuit in the Digilent board, and the demo of your new project will be graded.

c) Finally, the TA will ask each lab partner questions to check your knowledge and understanding of the project and Verilog, and you will receive a grade according to your answers.

As a result, your grade and your partner’s grade might not be the same grade, depending on your answers to the oral questions.

NOTES

--- Be sure to read and follow the Policies for CS223 labs.

--- An extensive tutorial is posted online at http://www.cs.bilkent.edu.tr/~oonder/CS223/ . You will find that this written tutorial provides vital information on how to create a project in Xilinx 11 and how to download it into the Digilent BASYS 2 FPGA board.

---Note that there is one mistake in the letters printed on the Digilent board. The pin number printed for SW0 is mistakenly written as M4, but actually it should written as P11, because it is connected to P11. You can make this change easy to remember by writing a small sticker and attaching it to the board by SW0

-- The PCs in the lab contain the Xilinx and Digilent software, installed, but these computers are extremely slow. You should use your own laptop computer to develop, test, debug and make ready the project before you come to the lab. On the day of your lab, you will be much better off to bring your own laptop computer with you, and to demonstrate the assignment using it. The idea is for your group to be able to bring your fully tested, debugged and working systems to lab, only to be graded.