CS223 - Digital Design - Fall 2022
ANNOUNCEMENTS
This is the website for CS223, Fall Semester 2022.
Course materials, slides, assignments, etc. will be accessible through Moodle.
If you have any questions regarding the Labs, please contact the TA(s) responsible for your specific Lab section.
Lab TA's announced.
Any further announcements will be posted here.
CLASS HOURS
Section 1: Mon 15:30-17:20, Thur 10:30-12:20 in EE-214; Lab: Mon 08:30-12:20 in EA-Z04
Section 2: Mon 15:30-17:20, Thur 10:30-12:20 in EE-214; Lab: Tue 08:30-12:20 in EA-Z04
Section 3: Tue 10:30-12:20, Thur 15:30-17:20 in EE-214; Lab: Wed 08:30-12:20 in EA-Z04
Section 4: Tue 10:30-12:20, Thur 15:30-17:20 in EE-214; Lab: Mon 13:30-17:20 in EA-Z04
Section 5: Wed 10:30-12:20, Fri 15:30, 17:20 in B-Z08; Lab: Fri 08:30-12:20 in EA-Z04
Section 6: Wed 10:30-12:20, Fri 15:30, 17:20 in B-Z08; Lab: Tue 13:30-17:20 in EA-Z04
LECTURERS
Alper Sarikan (Sec 5 and 6) Shervin R. Arashloo (Sec 1, 2, 3 and 4)
Office: EA-504 Office: EA-429
Office Hour: Fri 14:30 Office Hour: By appointment
E-mail: alper.sarikan bilkent.edu.tr E-mail: s.rahimzadeh cs.bilkent.edu.tr
Teaching Assistants
Head TA: Kaan Gönç (kaan.gonc-at-bilkent.edu.tr)
Section 1 (Monday Morning): Syed Asad Shah (asad.shah-at-bilkent.edu.tr)& Arda Sarp Yenicesu (sarp.yenicesu-at-bilkent.edu.tr)
Section 2 (Tuesday Morning): Saeed Karimi (saeed.karimi-at-bilkent.edu.tr)& Vahid Haratian (vahid.haratian-at-bilkent.edu.tr)
Section 3 (Wednesday Morning): Haya Shamim Khan Khattak (haya.khattak-at-bilkent.edu.tr)& Saeed Karimi (saeed.karimi-at-bilkent.edu.tr)
Section 4 (Monday Afternoon): Vahid Namakshenas (vahid-at-bilkent.edu.tr)& Sepehr Nourmohammadi (sepehr-at-bilkent.edu.tr)
Section 5 (Friday Morning): Vahid Namakshenas (vahid-at-bilkent.edu.tr)& Arda Sarp Yenicesu (sarp.yenicesu-at-bilkent.edu.tr)
Section 6 (Tuesday Afternoon): Barış Bilgin Şenol (bilgin.senol-at-bilkent.edu.tr)& Haya Shamim Khan Khattak (haya.khattak-at-bilkent.edu.tr)
COURSE DESCRIPTION
An introductory course in digital design, covering combinational and sequential circuits, memory and logic arrays and introduction to processor architecture, with a weekly lab. The SystemVerilog hardware description language is used throughout the semester to model and implement digital designs. Credits: 4 units
COURSE CONTENTS
Number systems, Binary numbers, Logic levels, transistors, gates, Boolean expressions. Combinational logic: Boolean algebra, simplification of Boolean expressions. Logic minimization with Karnaugh maps, don't-care conditions. Introduction to SystemVerilog. Combinational building blocks, multiplexers, decoders, propagation delays. SystemVerilog modeling. Sequential logic: SR latch, D-latch, D flip-flop, synchronous sequential circuits. Finite State Machine (FSM) design, Moore and Mealy models, state encodings, timing of sequential circuits. SystemVerilog modeling of sequential circuits. Signed numbers, Adders, ALU, comparators. Registers, register files. Counters, timers. High level state machines (HLSM), RTL design, RAM, ROM. FPGA, introduction to general purpose processor architecture.
PREREQUISITE
CS 101
TEXTBOOK & RECOMMENDED BOOK
David Money Harris, Sarah L. Harris, Digital Design and Computer Architecture, 2nd ed. Morgan Kaufmann, 2013. (Textbook)
Frank Vahid, Digital Design with RTL Design, VHDL and Verilog, 2nd ed. John Wiley, 2011. (Recommended)
Important Note:
Only original and unmarked textbooks will be allowed in the exams. If you have any notes/drawings/markings/etc. on your textbook, you will not be able to use it during the exams.
GRADING
Labs: 15 %
Project: 10 % (Report: 10%, Submission/Demo: 90%)
Quizzes: 15 % (possibly 3 quizzes with/without prior notice)
Midterm Exam: 30%
Final Exam: 30%
FZ POLICY
Students who fail to meet the following requirements will receive a grade of FZ:
Weighted average score of the midterm exam and quizzes (2*midterm-score + avg-quiz-score) /3: at least 40%.
Average score of the labs and project (avg-lab-score + project-score)/2: at least 50%.
Absent from no more than 1 Lab.
Only the grades until the FZ deadline will be considered while computing the average scores above. Students who receive FZ cannot attend the final exam.
TENTATIVE SCHEDULE (SUBJECT TO CHANGE)
WEEK | TOPICS COVERED | READINGS | LABS/PROJECT |
1 (15/09) | Introduction, digital values, number systems: decimal, binary and hexadecimal | Digital Design and Computer Architecture DDCA 1.1 - 1.4 | na |
2 (19/09) | Logic gates and physical characteristics, CMOS transistors, power consumption, Boolean algebra, Boolean equations, canonical forms | DDCA 1.5 - 1.9, 2.1 - 2.3 (excludes: 1.6.4, 1.6.5, 1.7.7, 1.7.8) | na |
3 (26/09) | Combinational logic, hardware reduction, X and Z logic values, introduction to SystemVerilog | DDCA 2.4 - 2.6, 4.1 - 4.2 | na |
4 (3/10) | Karnaugh maps, multiplexers and decoders, combinational timing and non-ideal behavior, SystemVerilog modeling | DDCA 2.7 - 2.9, 4.3 (excludes: 2.9.2) | na |
5 (10/10) | Latches & flip-flops, basic register, synchronous logic design, SystemVerilog modeling | DDCA 3.1 - 3.3, 4.4 - 4.5 | Lab #1 |
6 (17/10) | Finite state machines, FSM design, state encoding, Mealy vs. Moore models, SystemVerilog modeling | DDCA 3.4, 4.6 (excludes: 3.4.4) | Lab #2 |
7 (24/10) | FSM examples–No Classes on Thursday (27 Oct.), and Friday (28 Oct.) | | na |
8 (31/10) | Timing | DDCA 3.5 (excludes: 3.5.4, 3.5.5, 3.5.6, 3.6) | Lab #3 |
9 (07/11) | MIDTERM EXAM (12.11.2022; 09-12:30), Arithmetic functions, adders, subtractors, comparators, shifters, ALU, SystemVerilog models | DDCA 5.1 - 5.2 (excludes Prefix Adder, 5.2.6, 5.2.7) Vahid 4.3 - 4.4, 6.4 | na |
10 (14/11) | Registers, shift registers, counters, timers, SystemVerilog models | DDCA 5.4 Vahid 4.2, 4.8, 4.9 | na |
11 (21/11) | Memory components, static & dynamic RAM, ROM/PROM, SystemVerilog models | DDCA 5.5 Vahid 5.7 | Lab #4 |
12 (28/11) | High-level state machines (HLSM) | Vahid 5.1 - 5.5 | Lab #5 |
13 (05/12) | High-level state machines (HLSM) | Vahid 5.1 - 5.5 | Project |
14 (12/12) | HLSM examples | Vahid 5.1 - 5.5 | Project |
15 (19/12) | HLSM examples, FPGA | Vahid 5.1-5.5 Vahid 7.2-7.3 | Project Report & Demo
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