CS223 - Digital Design - Spring 2022

 

ANNOUNCEMENTS

  • This is the website for CS223, Spring Semester 2022.

  • Course materials, slides, assignments, etc. will be accessible through Moodle.

  • If you have any questions regarding the Labs, please contact the TA(s) responsible for your specific Lab section only.

  • The TA's responsible for each Lab section are announced. Your first point of contact regarding the Lab work should be the TA responsible for your sepcific Lab section. The head TA should be contacted in a next stage if you could not resolve the issue with your section TA.

  • Any further announcements will be posted here.

CLASS HOURS

Section 1:  Wed 10:30-12:20,   Fri 15:30, 17:20 in EE-05;        Lab: Thu 13:30-17:20 in EA-Z04

Section 2:  Wed 10:30-12:20,   Fri 15:30, 17:20 in EE-05;        Lab: Mon 13:30-17:20 in EA-Z04

Section 3:  Wed 10:30-12:20,   Fri 15:30, 17:20 in EE-05;        Lab: Thu 08:30-12:20 in EA-Z04

LECTURERS

 Alper Sarıkan (Sec 1-2-3)                               

Office: EA-504                                                

Office Hour: Fri 14:30                                    

E-mail: alper.sarikan@bilkent.edu.tr            

Teaching Assistants: Ahmet Burak Yıldırım, Hamza Islam, Kaan Gönç, Navid Ghamari, Osama Zafar, Saeed Karimi, Sepehr Nourmohammadi

COURSE DESCRIPTION

An introductory course in digital design, covering combinational and sequential circuits, memory and logic arrays and introduction to processor architecture, with a weekly lab. The SystemVerilog hardware description language is used throughout the semester to model and implement digital designs. Credits: 4 units

COURSE CONTENTS

Number systems, Binary numbers, Logic levels, transistors, gates, Boolean expressions. Combinational logic: Boolean algebra, simplification of Boolean expressions. Logic minimization with Karnaugh maps, don't-care conditions. Introduction to SystemVerilog. Combinational building blocks, multiplexers, decoders, propagation delays. SystemVerilog modeling. Sequential logic: SR latch, D-latch, D flip-flop, synchronous sequential circuits. Finite State Machine (FSM) design, Moore and Mealy models, state encodings, timing of sequential circuits. SystemVerilog modeling of sequential circuits. Signed numbers, Adders, ALU, comparators. Registers, register files. Counters, timers. High level state machines (HLSM), RTL design, RAM, ROM. FPGA, introduction to general purpose processor architecture.

PREREQUISITE

CS 101

TEXTBOOK & RECOMMENDED BOOK

  • David Money Harris, Sarah L. Harris, Digital Design and Computer Architecture, 2nd ed. Morgan Kaufmann, 2013. (Textbook)

  • Frank Vahid, Digital Design with RTL Design, VHDL and Verilog, 2nd ed. John Wiley, 2011. (Recommended)

Important Note:

Only original and unmarked textbooks will be allowed in the exams. If you have any notes/drawings/markings/etc. on your textbook, you will not be able to use it during the exams.

GRADING

  • Quizzes: 15 % (3 quizzes with prior notice)

  • Labs: 15 %

  • Project: 10 % (Report: 10%, Submission/Demo: 90%)

  • Midterm Exam: 30%

  • Final Exam: 30%

FZ POLICY

Students who fail to meet the following requirements will receive a grade of FZ:

  • Weighted average score of the midterm exam and quizzes (midterm-score + avg-quiz-score) /2: at least 40%.

  • Average score of the labs and project (avg-lab-score + project-score)/2: at least 50%.

  • Absent from no more than 1 Lab.

Only the grades until the FZ deadline will be considered while computing the average scores above. Students who receive FZ cannot attend the final exam.

TENTATIVE SCHEDULE (SUBJECT TO CHANGE)

WEEK

TOPICS COVERED

READINGS

LABS/

PROJECT

1

31/01

Introduction, digital values, number systems: decimal, binary and hexadecimal

Digital Design and Computer Architecture DDCA 1.1 - 1.4

 

2

07/02

Logic gates and physical characteristics, CMOS transistors, power consumption, Boolean algebra, Boolean equations, canonical forms

DDCA 1.5 - 1.9, 2.1 - 2.3 (excludes: 1.6.4, 1.6.5, 1.7.7, 1.7.8)

 

3

14/02

Combinational logic, hardware reduction,  X and Z logic values, introduction to SystemVerilog

DDCA 2.4 - 2.6, 4.1 - 4.2

 

4

21/02

Karnaugh maps, multiplexers and decoders, combinational timing and non-ideal behavior, SystemVerilog modeling

DDCA 2.7 - 2.9, 4.3          (excludes: 2.9.2)

Lab #1

Sec 1,2,3,4

5

28/02

Latches & flip-flops, basic register, synchronous logic design, SystemVerilog modeling

DDCA 3.1 - 3.3, 4.4 - 4.5

Lab #2

Sec 1,2,3,4

6

07/03

Finite state machines, FSM design, state encoding, Mealy vs. Moore models, SystemVerilog modeling

*No Classes on Thursday, Friday*

DDCA 3.4, 4.6                  (excludes: 3.4.4)

 

7

14/03

FSM examples

 

Lab #3

Sec 1,2,3,4

8

21/03

Timing

DDCA 3.5  (excludes:  3.5.4, 3.5.5, 3.5.6, 3.6)

 

9

28/03

Arithmetic functions, adders, subtractors, comparators, shifters, ALU, SystemVerilog models

*MIDTERM EXAM*

DDCA 5.1 - 5.2  (excludes Prefix Adder, 5.2.6, 5.2.7)

Vahid 4.3 - 4.4, 6.4

 

10

04/04

Registers, shift registers, counters, timers, SystemVerilog models

DDCA 5.4

Vahid 4.2, 4.8, 4.9

Lab #4

Sec 1,2,3,4,5,6

11

11/04

Memory components, static & dynamic RAM, ROM/PROM,  SystemVerilog models

DDCA 5.5

Vahid 5.7

Lab #5

Sec 1,2,3,4,5,6

12

18/04

High-level state machines (HLSM)

Vahid 5.1 - 5.5

Project

13

25/04

High-level state machines (HLSM)

Vahid 5.1 - 5.5

Project

14

02/05

HLSM examples

*No Classes on Monday, Tuesday, Wednesday*

Vahid 5.1 - 5.5

Project

15

09/05

HLSM examples, FPGA

Vahid 5.1 - 5.5

Vahid 7.2 - 7.3

Project Report & Demo