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CS223 - Digital Design - Spring 2024
ANNOUNCEMENTS
This is the website for CS223, Spring Semester 2024.
Course materials, slides, assignments, etc. will be accessible via Moodle.
If you have any questions regarding the Labs, please contact the TA(s) responsible for your specific Lab section.
Any further announcements will be posted here.
GenAI Policy
Using AI models for coursework including assignments, lab work, projects, exams and quizzes is completely prohibited.
CLASS HOURS
Section 1: Wed. 11:30-12:20, Fri. 15:30-17:20 in V-01; Lab: Thur. 13:30-17:20 in EA-Z04
Section 2: Wed. 11:30-12:20, Fri. 15:30-17:20 in V-01; Lab: Mon. 13:30-17:20 in EA-Z04
LECTURER
Shervin R. Arashloo
Office: EA-429
Office Hour: By appointment
E-mail: s.rahimzadeh-at-cs.bilkent.edu.tr
Teaching Assistants
Head TA: Vahid Namakshenas (vahid-at-bilkent.edu.tr)
Section 1, Thursdays 13:30-17:20
Vahid Namakshenas (vahid -at- bilkent.edu.tr)
Emir Türkölmez (emir.turkolmez -at- bilkent.edu.tr)
Muhammed (m.yildirim -at- bilkent.edu.tr)
Kerem (kerem.bayramoglu -at- bilkent.edu.tr)
Section 2, Mondays 13:30-17:20
Buğra Aksoy (bugra.aksoy -at- ug.bilkent.edu.tr)
Deniz Çatakoğlu (deniz.catakoglu -at- ug.bilkent.edu.tr)
Kerem Bayramoğlu(kerem.bayramoglu -at- bilkent.edu.tr)
Muhammed Yıldırım (m.yildirim -at- bilkent.edu.tr)
Emre Kavgacı (emre.kavgaci -at- ug.bilkent.edu.tr)
Huzaifa Huzaifa (huzaifa -at- bilkent.edu.tr)
COURSE DESCRIPTION
An introductory course in digital design, covering combinational and sequential circuits, memory and logic arrays and introduction to processor architecture, with a weekly lab. The SystemVerilog hardware description language is used throughout the semester to model and implement digital designs. Credits: 4 units
COURSE CONTENTS
Number systems, Binary numbers, Logic levels, transistors, gates, Boolean expressions. Combinational logic: Boolean algebra, simplification of Boolean expressions. Logic minimization with Karnaugh maps, don't-care conditions. Introduction to SystemVerilog. Combinational building blocks, multiplexers, decoders, propagation delays. SystemVerilog modeling. Sequential logic: SR latch, D-latch, D flip-flop, synchronous sequential circuits. Finite State Machine (FSM) design, Moore and Mealy models, state encodings, timing of sequential circuits. SystemVerilog modeling of sequential circuits. Signed numbers, Adders, ALU, comparators. Registers, register files. Counters, timers. High level state machines (HLSM), RTL design, RAM, ROM. FPGA, introduction to general purpose processor architecture.
PREREQUISITE
CS 101
TEXTBOOK & RECOMMENDED BOOK
David Money Harris, Sarah L. Harris, Digital Design and Computer Architecture, 2nd ed. Morgan Kaufmann, 2013. (Textbook)
Frank Vahid, Digital Design with RTL Design, VHDL and Verilog, 2nd ed. John Wiley, 2011. (Recommended)
Important Note:
Only original and unmarked textbooks will be allowed in the midterm/final exam. If you have any notes/drawings/markings/etc. on your textbook, you will not be able to use it during the midterm/final exam.
GRADING
Labs: 15 %
Project: 10 % (Report: 10%, Submission/Demo: 90%)
Quizzes: 15 % (possibly 3 quizzes with/without prior notice)
Midterm Exam: 30%
Final Exam: 30%
FZ POLICY
Students who fail to meet the following requirements will receive an FZ grade:
Weighted average score of the midterm exam and quizzes (2*midterm-score + avg-quiz-score) /3: at least 40%.
Average score of the labs and project (avg-lab-score + project-score)/2: at least 50%.
Absent from no more than 1 Lab.
Only the grades until the FZ deadline will be considered while computing the average scores above. Students who receive FZ cannot attend the final exam.
TENTATIVE SCHEDULE (SUBJECT TO CHANGE)
| WEEK | TOPICS COVERED | READINGS | LABS/PROJECT |
1
(29/01) | Introduction, digital values, number systems: decimal, binary and hexadecimal | Digital Design and Computer Architecture DDCA 1.1 - 1.4 | na |
2
(05/02) | Logic gates and physical characteristics, CMOS transistors, power consumption, Boolean algebra, Boolean equations, canonical forms | DDCA 1.5 - 1.9, 2.1 - 2.3 (excluding: 1.6.4, 1.6.5, 1.7.7, 1.7.8) | na |
3
(12/02) | Combinational logic, hardware reduction, X and Z logic values, introduction to SystemVerilog | DDCA 2.4 - 2.6, 4.1 - 4.2 | na |
4
(19/02) | Karnaugh maps, multiplexers and decoders, combinational timing and non-ideal behavior, SystemVerilog modeling | DDCA 2.7 - 2.9, 4.3 (excluding: 2.9.2) | na |
5
(26/02) | Latches & flip-flops, basic register, synchronous logic design, SystemVerilog modeling | DDCA 3.1 - 3.3, 4.4 - 4.5 | Lab #1 |
6
(04/03) | Finite state machines, FSM design, state encoding, Mealy vs. Moore models, SystemVerilog modeling | DDCA 3.4, 4.6 (excluding: 3.4.4) | na |
7
(11/03) | FSM examples | na | Lab #2 |
8
(18/03) | Timing | DDCA 3.5 (excluding: 3.5.4, 3.5.5, 3.5.6, 3.6) | Lab #3 |
9
(25/03) | Arithmetic functions, adders, subtractors, comparators, shifters, ALU, SystemVerilog models
MIDTERM EXAM | DDCA 5.1 - 5.2 (excluding Prefix Adder, 5.2.6, 5.2.7)
Vahid 4.3 - 4.4, 6.4 | na |
10
(01/04) | Registers, shift registers, counters, timers, SystemVerilog models | DDCA 5.4
Vahid 4.2, 4.8, 4.9 | The project will be released on Moodle |
11
(08/04) | No Classes
(Feast of Ramadan holiday) | na | na |
12
(15/04) | Memory components, static & dynamic RAM, ROM/PROM, SystemVerilog models | DDCA 5.5
Vahid 5.7 | Lab #4 |
13
(22/04) | High-level state machines (HLSM)
No classes on Wednesday, 1 May 2024 (Labor and Solidarity Day holiday) | Vahid 5.1 - 5.5 | na |
14
(29/04) | High-level state machines (HLSM) | Vahid 5.1 - 5.5 | Lab #5 |
15
(06/05) | HLSM examples | Vahid 5.1 - 5.5 | Project Demo |
16
(13/05) | HLSM examples | Vahid 5.1-5.5
Vahid 7.2-7.3 | na
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