Department of Computer Engineering
S E M I N A R
Latency-Aware Heterogeneous Network-on-Chip Arcitecture Design
Computer Engineering Department
This thesis introduces a Network-on-Chip(NoC) design technique where biologically inspired evolutionary algorithm and 2 dimensional rectangle packing algorithms are used to place processing elements which have various properties into a constrained NoC area according tasks generated by Task Graph For Free(TGFF). TGFF is one of the pseudo-random task-graph generator for use in scheduling and allocation research area. These tasks are used in our algorithms to minimize the maximum latency time between heterogeneous Chip Multiprocessors(CMP) by considering communication cost which is a big issue to care in multi-core architecture is came up to the optimum result within a considerably succinct time.
DATE: 27 June, 2011, Monday @ 10:30