Bilkent University
Department of Computer Engineering


Architecting and Exploiting Asymmetry in Multi-Core Architectures


Dr. Onur Mutlu
Carnegie Mellon University
Electrical and Computer Engineering

This talk will cover some of our recent work on designing high-performance and efficient heterogeneous multi-core systems. I will focus on several ideas that both exploit heterogeneity in hardware design and application behavior to solve two different problems: thread serialization in parallel programs and high-performance memory scheduling. If time permits, I will also briefly delve into the design of heterogeneous shared resources, such as interconnects, memory controllers, and main memory.

In the main part of the talk, I will discuss our new approaches to using multiple different types of cores to accelerate bottleneck program portions using two hardware/software cooperative mechanisms as examples. Accelerated Critical Sections (ACS) paradigm ships critical sections to fast cores of a heterogeneous multi-core processor to reduce serialization and improve locality. Bottleneck Identification and Scheduling (BIS) identifies and accelerates the most critical synchronization bottlenecks in multithreaded applications by shipping bottleneck code portions to fast cores of a heterogeneous multi-core processor. Both paradigms are examples of Staged Execution, i.e., dividing a program into segments and executing each segment at the core that has the data and/or functionality to best run that segment.I will show that the benefit of such staged execution models are limited by inter-segment data transfers that happen between cores and describe a new mechanism that overcomes this limitation by automatically marshaling data between cores executing different segments.

In the second part of the talk, if time permits, I will describe memory controller designs that exploit heterogeneity in the behavior of concurrently executing threads to improve system performance and fairness. The main idea of one design is to divide threads into two separate clusters and employ different memory request scheduling policies in each cluster such that the needs of different kinds of threads are served separately in both homogeneous and heterogeneous multi-core systems. Another design prioritizes the critical threads in a multithreaded application, using bottleneck identification mechanisms similar to the BIS paradigm. Our evaluations show these heterogeneous memory control policies outperform all previous memory schedulers in both performance and fairness.

Bio: Onur Mutlu is an Assistant Professor of ECE (and by courtesy CSD) at Carnegie Mellon University. His broader research interests are in computer architecture and systems, especially in the interactions between languages, operating systems, compilers, and microarchitecture.

He enjoys teaching and researching important and relevant problems in computer architecture, including problems related to the design of memory systems, multi-core architectures, and scalable and efficient systems. He obtained his PhD and MS in ECE from the University of Texas at Austin (2006) and BS degrees in Computer Engineering and Psychology from the University of Michigan, Ann Arbor. Prior to Carnegie Mellon, he worked at Microsoft Research (2006-2009), Intel Corporation, and Advanced Micro Devices. He was a recent recipient of the 2011 IEEE Computer Society Young Computer Architect Award, 2012 CMU College of Engineering George Tallman Ladd Research Award, 2012 Intel Early Career Faculty Honor Award, Microsoft Gold Star Award, best paper awards at ASPLOS, VTS and ICCD, and a number of “computer architecture top pick” paper selections by the IEEE Micro magazine. For more information, please see his webpage at


DATE: 28 December, 2012, Friday @ 10:30