Bilkent University
Department of Computer Engineering


Hardware Mechanisms to Alleviate the Side Effects of the Cache Coherent Protocol in Tiled Chip Multiprocessors


Mahmut Sami Dikici
MSc Student
Computer Engineering Department
Bilkent University

Over the last decade, processors with very powerful, more complex and more power-hungry single superscalar core running at very high clock speeds have been replaced by chip multiprocessor(CMP) systems, CMPs’ ability of achieving high performance for parallel applications greatly relies on how effectively their cores can communicate with each other through on-chip interconnects.

Caching is crucial to reducing memory latency in CMPs, thus each core is generally integrated with a private cache. Private caches, however, may create a coherence problem, which is generally handled with a hardware-managed coherence protocol in CMPs. While the coherency protocol keeps the multiple copies of the same data consistent across different core’s private caches, it introduces ramifications on performance, area costs and communication bandwidth requirements as well as on power consumption. Unfortunately, traditional coherence protocols do not differentiate between communicating data – shared data that is updated by one core and read by another core, each data goes through the same protocol, making the aforementioned ramifications quite serious.

In this work, we present some hardware approaches to alleviate the side effects of directory based cache coherence protocols implemented on CMPs with mesh on-chip interconnect. During runtime, the behavior of the hardware to loads/stores will depend on the type of corresponding data: Loads/Stores related to communicating data will be managed by the underlying coherence protocol, and the memory access instructions for the regular data will be bypass the coherence protocol, reducing the side effects of the coherence protocol.


DATE: 01 April, 2013, Monday @ 16:40