Department of Computer Engineering
MS THESIS PRESENTATION
Adaptive Thread and Memory Access Scheduling in Chip Multiprocessors
Computer Engineering Department
The full potential of chip multiprocessors remains unexploited due to architecture oblivious thread schedulers used in operating systems, and thread-oblivious memory access schedulers used in off-chip main memory controllers. For the thread scheduling, we introduce an adaptive cache-hierarchy-aware scheduler that tries to schedule threads in a way that inter-thread contention is minimized. A novel multi-metric scoring scheme is used that specifies the L1 cache access characteristics of a thread. The scheduling decisions are made based on multi-metric scores of threads. For the memory access scheduling, we introduce an adaptive compute-phase prediction and thread prioritization scheme that efficiently categorize threads based on execution characteristics and provides fine-grained prioritization that allows to differentiate threads and prioritize their memory access requests accordingly.
Keywords: Adaptive scheduling, chip multiprocessors, inter-thread contention, thread phase prediction, multi-metric scoring
DATE: 11 July, 2013, Thursday @ 13:30