Department of Computer Engineering
S E M I N A R
Performance Evaluation of Sparse Matrix-Vector Multiplication on Intel Xeon Phi Architecture
Mustafa Ozan Karsavuran
Computer Engineering Department
Intel Xeon Phi is the new family of processors that enables 1 Teraflop/s performance from a single processor. Initial models of the Intel Xeon Phi processor family have 60 small cores each supporting 4 hardware threads. These architectural properties definitely require efficient parallelization of the application. In this work, we investigate efficient parallelization of sparse matrix-vector multiplication (SpMV) operation, which is a widely kernel operation used in scientific computing. Our aim is to find effective parallelization models and methods for providing scalability of the SpMV operation up to 240 threads.
DATE: 24 March, 2014, Monday @ 16:10