Department of Computer Engineering
CS 590 SEMINAR
Energy Efficient Architecture for Graph Analytics Accelerators
Computer Engineering Department
Specialized hardware accelerators can significantly improve the performance and power efficiency of compute systems. In this presentation, we will focus on hardware accelerators for graph analytics applications and propose a configurable architecture template that is specifically optimized for iterative vertex-centric graph applications with irregular access patterns and asymmetric convergence. The proposed architecture addresses the limitations of the existing multi-core CPU and GPU architectures for these types of applications.
The SystemC-based template we provide can be customized easily for different vertex-centric applications by inserting application-level data structures and functions. After that, a cycle-accurate simulator and RTL can be generated to model the target hardware accelerators. Our experiments showed that the hardware accelerators generated by our template can outperform a 24 core high end server CPU system by up to 3x in terms of performance with up to 65x better power consumption and significantly smaller area.
DATE: 11 April, 2016, Monday @ 16:00