Department of Computer Engineering
MS THESIS PRESENTATION
Accelerator Design For Graph Analytics
(Supervisor: Assoc. Prof. Dr. Özcan Öztürk)
Computer Engineering Department
With the increase in data available online, data analysis became a significant problem in today's datacenters. Moreover, graph analytics applications are one of the significant application domains in big data era. However, traditional architectures such as CPUs and GPUs fail to serve the needs of graph applications. Unconventional properties of graph applications such as irregular memory accesses, load balancing, and irregular computations challenges current computing systems that either throughput oriented or built on top of traditional locality based memory subsystems.
On the other hand, an emerging technique hardware customization, can help us to overcome these problems and they are expected to be energy efficient. Considering the power wall, hardware customization becomes more desirable.
In this thesis, we propose a hardware accelerator framework that is capable of handling irregular, vertex centric, and asynchronous graph applications. Developed high level SystemC models gives an abstraction to the programmer and programmer is able to implement the hardware without extensive knowledge on the underlying architecture. With the given template programmers are not limited to a single application since they can develop any graph applications as long as it fits to given template abstract. Beside, ability to develop different applications, given template also decreases time spent to develop and test different accelerators. Additionally, an extensive experimental study shows that proposed template can outperform a high-end 24 cores CPU system upto 3x with upto 65x power efficiency.
DATE: 14 June, 2016, Tuesday @ 09:30