Department of Computer Engineering
CS 590 SEMINAR
Accelerating Sparse Matrix-Vector Multiplication on FPGA
Computer Engineering Department
Sparse matrix-vector multiplication (SpMV) is a bottleneck operation in many scientific and engineering computations. The irregular memory access pattern in SpMV makes obtaining high performance challenging. Due to the fine granular random memory accesses, there occurs a significant waste of DRAM traffic and poor bandwidth utilization. In this study, we aim to accelerate sparse matrix-vector multiplication on FPGA by optimizing DRAM communication, by not writing to output vector directly, but first to intermediate buckets, and then to output vector, which increases the spatial locality.
DATE: 09 December 2019, Monday @ 16:10