Department of Computer Engineering
MS THESIS PRESENTATION
EFFICIENT HLS-BASED IMPLEMENTATION OF SPARSE MATRIX-VECTOR MULTIPLICATION ON FPGA
(Supervisor:Assoc. Prof. Dr. M. Mustafa Özdal)
Computer Engineering Department
Sparse Matrix-Vector Multiplication (SpMV) is an important core kernel used in many scientific and engineering applications. SpMV suffers from poor spatial locality and low computation-to-communication ratio due to its inherent irregular memory access patterns. This causes a significant waste of DRAM traffic and poor bandwidth utilization. Recently published Propagation Blocking (PB) methodology tackles this communication bottleneck by dividing the execution into binning and accumulation phases in a scatter-gather paradigm, allowing higher spatial locality in the cost of more read/write requests. Adopting PB approach, we implement two FPGA kernels for binning and accumulation phases using high-level synthesis, which can be run together sequentially or used with heterogeneous designs independently. Experimental results show that our design performs comparable to CPU baselines and outperforms naive FPGA baseline in terms of execution time and throughput.
DATE: 30 September 2021, Thursday @ 18:30