Bilkent University
Department of Computer Engineering
M.S.THESIS PRESENTATION
RISC-V Based Accelerator for Depthwise Separable Convolutions in Edge AI
Muhammed Yıldırım
Master Student
(Supervisor:Prof.Dr.Uğur Güdükbay)
Computer Engineering Department
Bilkent University
Abstract: The increasing demand for on-device intelligence in Edge Artificial Intelligence (AI) applications requires the efficient execution of modern Convolutional Neural Networks (CNNs). While lightweight architectures like MobileNetV2 employ Depthwise Separable Convolutions (DSC) to reduce computational complexity, their multi-stage design introduces a critical performance bottleneck inherent to layer-by-layer execution. This approach incurs high energy and latency costs due to intermediate feature map transfers. To address this memory wall, we propose a hardware accelerator architecture that employs a fused pixel-wise dataflow. Implemented as a Custom Function Unit (CFU) for a RISC-V processor, our architecture eliminates memory accesses for intermediate feature maps, reducing data movement by up to 87% compared to conventional layer-by-layer execution. It computes each output pixel fully across all DSC stages, including expansion, depthwise, and projection. This is achieved by streaming data through a tightly coupled pipeline without requiring memory writes. Evaluated on a Xilinx Artix-7 FPGA, our design achieves a speedup of up to 59.3x over the CPU-only RISC-V baseline execution. Furthermore, post-layout ASIC implementation in Cadence Innovus achieves a compact 0.449 mm^2 footprint with 1.25 W total power at 2 GHz in 28 nm TSMC HPC technology. The results confirm the feasibility of a zero-buffer dataflow within an Edge AI resource envelope, demonstrating an effective strategy to overcome the memory wall in hardware accelerators.
DATE: July 14, Tuesday @ 11:00
Place: EA 409