The Verilog models you develop need to be tested with a simulator. Several Verilog simulators are discussed below.
SILOS: this simulator is easy to use, with a fast learning curve for new users. A free demo version is available from this Silos Resources link, but this free version has a 400 line limitation--it will not simulate more than 400 lines of Verilog code. (Of course, there is a full version which has no such limit, but it is not free.) Possible workarounds include condensing code by combining modules, and even merging lines together. Due to a change in Windows in handling stack, it doesn't work directly with versions after Win XP SP2 (i.e. not with Windows XP Service Pack 3, or Vista or Windows 7). But using virtual machine software, such as Oracle VirtualBox, you can virtualize the machine and run Windows XP as a “guest” operating system. SILOS works in such an environment. It also works in Linux OS environments, using Wine (a Windows emulator).
ModelSim: this simulator is made available from Xilinx, both on the ISE CD-ROMS, and with the downloadable Webpacks. You can actually download the Modelsim version 3.6 from here. (An older Xilinix version that works with it can be downloaded here). There is a cost to obtain a full license from ModelSim, but the Starter license is free to all who register for it. There seems to be no limitation of the number of lines of Verilog code, except that big programs simulate very slowly in ModelSim with the Starter license.
Icarus Verilog: This open-source Verilog simulator runs on Linux OS environments. There is not a limit to the number of lines that can be simulated with the free edition.
SynaptiCAD's Verilogger: this simulator for Verilog is available free in a version that allows up to 1000 lines of code in the model. Note that one student who used it found that "pc <= 0" was required for initialization, rather than "pc = 0".
A list of Verilog simulators, with information and links, is available on Wikipedia.