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CS223 - Digital Design - Spring 2026
ANNOUNCEMENTS
This is the website for CS223, Spring Semester 2026.
Course materials, slides, assignments, etc. will be accessible via Moodle.
If you have any questions regarding the Labs, please contact the TA(s) responsible for your specific Lab section.
Any further announcements will be posted here.
LAB RULES
Students must strictly adhere to the following rules when using the laboratory for this course; otherwise there would be grade penalties.
No eating or drinking is allowed in the lab.
Each Lab board is associated with a number. Once you finished your work, you must place back the board in an orderly manner.
When you are done, return IC parts into the IC boxes, where you have taken them first.
Do not unplug any cables (ethernet, monitor, etc.).
Return all your processes to their first state before you leave the laboratory.
GenAI Policy
We follow the Generative AI policy guideline of Bilkent University which can be found here.
CLASS HOURS
Section 1: Mon. 8:30-10:20, Wed. 13:30-15:20 in EB-204; Lab: Wed. 8:30-12:20 in EA-Z04
Section 2: Mon. 8:30-10:20, Wed. 13:30-15:20 in EB-204; Lab: Mon. 13:30-17:20 in EA-Z04
Section 3: Wed. 10:30-12:20, Fri. 15:30-17:20 in EA-Z01; Lab: Thur. 8:30-12:20 in EA-Z04
Section 4: Wed. 10:30-12:20, Fri. 15:30-17:20 in EA-Z01; Lab: Tue. 8:30-12:20 in EA-Z04
LECTURER
Shervin R. Arashloo
Office: EA-429
Office Hour: By appointment
E-mail: s.rahimzadeh [at] cs.bilkent.edu.tr
TEACHING ASSISTANTS
Head TA: Muhammed Yıldırım (m.yildirim -at- bilkent.edu.tr)
Section 1: Emir Türkölmez (emir.turkolmez -at- bilkent.edu.tr), Zahra Safdari Fesaghandis (zahra.safdari -at- bilkent.edu.tr)
Section 2: Göktuğ Serdar Yıldırım (serdar.yildirim -at- bilkent.edu.tr), Zahra Safdari Fesaghandis (zahra.safdari -at- bilkent.edu.tr)
Section 3: Elyar Esmaeilzadeh (elyar -at- bilkent.edu.tr), Göktuğ Serdar Yıldırım (serdar.yildirim -at- bilkent.edu.tr)
Section 4: Elyar Esmaeilzadeh (elyar -at- bilkent.edu.tr), Emir Türkölmez (emir.turkolmez -at- bilkent.edu.tr)
Grader: Vahid Namakshenas (vahid -at- bilkent.edu.tr)
COURSE DESCRIPTION
An introductory course in digital design, covering combinational and sequential circuits, memory and logic arrays and introduction to processor architecture, with a weekly lab. The SystemVerilog hardware description language is used throughout the semester to model and implement digital designs. Credits: 4 units
COURSE CONTENTS
Number systems, Binary numbers, Logic levels, transistors, gates, Boolean expressions. Combinational logic: Boolean algebra, simplification of Boolean expressions. Logic minimization with Karnaugh maps, don't-care conditions. Introduction to SystemVerilog. Combinational building blocks, multiplexers, decoders, propagation delays. SystemVerilog modeling. Sequential logic: SR latch, D-latch, D flip-flop, synchronous sequential circuits. Finite State Machine (FSM) design, Moore and Mealy models, state encodings, timing of sequential circuits. SystemVerilog modeling of sequential circuits. Signed numbers, Adders, ALU, comparators. Registers, register files. Counters, timers. High level state machines (HLSM), RTL design, RAM, ROM. FPGA, introduction to general purpose processor architecture.
PREREQUISITE
CS 101
TEXTBOOK & RECOMMENDED BOOK
David Money Harris, Sarah L. Harris, Digital Design and Computer Architecture, 2nd ed. Morgan Kaufmann, 2013. (Textbook)
Frank Vahid, Digital Design with RTL Design, VHDL and Verilog, 2nd ed. John Wiley, 2011. (Recommended)
Important Note:
Textbooks or any other material will NOT be allowed in the quizzes and exams.
GRADING
FZ POLICY
Students who fail to meet the following requirements will receive an FZ grade:
Weighted average score of the midterm exam and quizzes (2*midterm-score + avg-quiz-score) /3: at least 40%.
Average score of the labs: at least 50%.
Absent from no lab (only the tutorial lab session may be missed).
Only the grades until the FZ deadline will be considered while computing the average scores above. Students who receive FZ cannot attend the final exam.
Late submissions policy
We follow no extension policy.
TENTATIVE SCHEDULE (SUBJECT TO CHANGE)
| WEEK | TOPICS COVERED | READINGS | LABS |
1
(26/01) | Digital values, number systems: decimal, binary and hexadecimal | Digital Design and Computer Architecture DDCA 1.1 - 1.4 | na |
2
(02/02) | Logic gates and physical characteristics, CMOS transistors, power consumption, Boolean algebra, Boolean equations, canonical forms | DDCA 1.5 - 1.9, 2.1 - 2.3 (excluding: 1.6.4, 1.6.5, 1.7.7, 1.7.8) | na |
3
(09/02) | Combinational logic, hardware reduction, X and Z logic values, introduction to SystemVerilog | DDCA 2.4 - 2.6, 4.1 - 4.2 | na |
4
(16/02) | Karnaugh maps, multiplexers and decoders, combinational timing and non-ideal behavior, SystemVerilog modeling | DDCA 2.7 - 2.9, 4.3 (excluding: 2.9.2) | Lab Tutorial |
5
(23/02) | Latches & flip-flops, basic register, synchronous logic design, SystemVerilog modeling | DDCA 3.1 - 3.3, 4.4 - 4.5 | na |
6
(02/03) | Finite state machines, FSM design, state encoding, Mealy vs. Moore models, SystemVerilog modeling | DDCA 3.4, 4.6 (excluding: 3.4.4) | Lab #1 |
7
(09/03) | FSM examples | na | na |
8
(16/03) | no classes | na | na |
9
(23/03) | Timing | DDCA 3.5 (excluding: 3.5.4, 3.5.5, 3.5.6, 3.6) | Lab #2 |
10
(30/03) | Arithmetic functions, adders, subtractors, comparators, shifters, ALU, SystemVerilog models | DDCA 5.1 - 5.2 (excluding Prefix Adder, 5.2.6, 5.2.7)
Vahid 4.3 - 4.4, 6.4 | na |
11
(06/04) | Registers, shift registers, counters, timers, SystemVerilog models | DDCA 5.4
Vahid 4.2, 4.8, 4.9 | Lab #3 |
12
(13/04) | Memory components, static & dynamic RAM, ROM/PROM, SystemVerilog models | DDCA 5.5
Vahid 5.7 | na |
13
(20/04) | High-level state machines (HLSM)
| Vahid 5.1 - 5.5 | na |
14
(27/04) | High-level state machines (HLSM)
no classes on Friday | Vahid 5.1 - 5.5 | na |
15
(04/05) | HLSM examples | Vahid 5.1 - 5.5 | na |
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